View HT82V24_3150696.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT82V24 16-bit, 15msps, 3-channel ccd/cis analog signal processor block diagram rev. 1.00 1 september 7, 2005 features operating voltage: 5v low power consumption at 380mw (typ.) power-down mode: under 2 a (typ.) 16-bit 15 msps a/d converter supports adi/wm mode data output formats selec - tion guaranteed won t miss codes 1~6x programmable gain correlated double sampling 300mv programmable offset input clamp circuitry internal voltage reference multiplexed byte/nibble-wide output (8 2/4 4 format) programmable 3-wire serial interface 3v/5v digital i/o compatibility 3-channel operation up to 5 msps for each channel 2-channel (even-odd) operation up to 7.5 msps for each channel 1-channel operation up to 15 msps 20/28-pin sop/ssop package (pb-free on request)

! ! " # $ % % & # " ' ! ( ' ) * * + , + * * * * * " * " * " ) + + , - . * - / - ) ) , - ) , general description the HT82V24 is a complete analog signal processor for ccd imaging applications. it features a 3-channel archi- tecture designed to sample and condition the outputs of tri-linear color ccd arrays. each channel consists of an input clamp, correlated double sampler (cds), offset dac and programmable gain amplifier (pga), and a high performance 16-bit a/d converter. the cds amplifiers may be disabled for use with sen- sors such as contact image sensors (cis) and cmos active pixel sensors, which do not require cds. the 16-bit digital output is multiplexed into an 8/4-bit output word that is accessed using two/four read cycles. the internal registers are programmed through a 3-wire serial interface, which provides gain, offset and operat- ing mode adjustments. HT82V24 supports adi/wm mode data output formats. the HT82V24 operates from a single 5v power supply, typically consumes 380mw of power. applications flatbed document scanners film scanners digital color copiers multifunction peripherals
pin assignment pin description pin name i/o description cdsclk1/vsmp di cds reference clock pulse input adi mode: cdsclk1 wm mode: vsmp cdsclk2 di cds data clock pulse input adcclk di a/d sample clock input for 3-channels mode oe di output enable, active low dvdd p digital power dvss p digital ground d7~d0 do digital data output sdata di/do serial data input/output sclk di clock input for serial interface sload di serial interface load pulse avss p analog ground avdd p analog supply refb ao reference decoupling reft ao reference decoupling vinb ai analog input, blue cml ao internal reference output ving ai analog input, green offset ao clamp bias level decoupling vinr ai analog input, red absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +5.5v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0.3v to v dd +0.3v operating temperature .......................... 25 cto75 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. HT82V24 rev. 1.00 2 september 7, 2005 / $ / 0 / / 1 / & / / / / / 2 $ 0 1 / & 1 0 $ 2 / & * * * " ) + + , * " * " + , + * * ) - , - . * - / - ) * * 0 % 3 4 1 & / 2 % 3 4

/ 2 $ 0 1 & / / & 1 0 $ 2

* * * - * * 0 1 & * " ) + + , + , + * * ) - ,
d.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions logic inputs v ih high level input voltage 0.8 dv dd v v il low level input voltage 0.2 dv dd v i ih high level input current 10 a i il low level input current 10 a c in input capacitance 10 pf logic outputs v oh high level output voltage dv dd 0.5 v v ol low level output voltage 0.5 v i oh high level output current 5v 0.7 ma i ol low level output current 5v 1.1 ma a.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions power supplies av dd analog power 4.75 5 5.25 v dv dd digital i/o power 3 5 5.25 v maximum conversion rate f max3 3-channel mode with cds 15 msps f max2 2-channel mode with cds 15 msps f max1 1-channel mode with cds 15 msps accuracy (entire signal path) adc resolution 16 bits integral nonlinear (inl) 32 lsb differential nonlinear (dnl) 1 1 lsb offset error 150 150 mv gain error 5 %fsr analog inputs r fs full-scale input range 2.0/3.0* vp-p v i input limits a vss -0.3 a vdd +0.3 v c i input capacitance 10 pf i i input current 10 na amplifiers pga gain at minimum 1 v/v pga gain at maximum 6 v/v pga gain resolution 6 bits programmable offset at minimum 300 mv programmable offset at maximum 300 mv offset resolution 9 bits HT82V24 rev. 1.00 3 september 7, 2005
symbol parameter test conditions min. typ. max. unit v dd conditions temperature range t a operating 0 70 c power consumption p tot3 total power consumption (3ch) 380 mw p tot2 total power consumption (2ch) 340 mw p tot1 total power consumption (1ch) 300 mw note: * means the full-scale input range select by configuration register timing specification symbol parameter min. typ. max. unit clock parameters t pra 3-channel pixel rate 200 ns t prb 2-channel (even-odd) pixel rate 133 ns t prc 1-channel pixel rate 66 ns t adclk adcclk pulse width 33 ns t c1 cdsclk1 pulse width 15 30 ns t c2 cdsclk2 pulse width 15 30 ns t c1c2 cdsclk1 falling to cdsclk2 rising 0 ns t adc2 adcclk rising to cdsclk2 falling 0 ns t c2adr cdsclk2 rising to adcclk rising 5 ns t c2adf cdsclk2 falling to adcclk falling 30 ns t c2c1 cdsclk2 falling to cdsclk1 rising 30 ns t ad analog sampling delay 5 ns serial interface f sclk maximum sclk frequency 10 mhz t ls sload to sclk setup time 10 ns t lh sclk to sload hold time 10 ns t ds sdata to sclk rising setup time 10 ns t dh sclk rising to sdata hold time 10 ns t rdv falling to sdata valid 10 ns data output t od output delay 12 ns HT82V24 rev. 1.00 4 september 7, 2005
HT82V24 rev. 1.00 5 september 7, 2005 functional description integral nonlinear (inl) integral nonlinear error refers to the deviation of each in - dividual code from a line drawn from zero scale through a positive full scale. the point used as zero scale occurs 1 / 2 lsb before the first code transition. a positive full scale is defined as a level 1 / 2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinear (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. no missing codes guaranteed for the 16-bit resolution indicates that all the 65536 codes respectively, are present in the over-all operating range. offset error the first adc code transition should occur at a level 1 / 2 lsb above the nominal zero scale voltage. the offset error is the deviation of the actual first code transition level from the ideal level. gain error the last code transition should occur for an analog value of 1 / 2 lsb below the nominal full-scale voltage. gain error is the deviation of the actual difference be - tween the first and the last code transitions and the ideal difference between the first and the last code transi - tions. sampling delay the sampling delay is the time delay that occurs when a sampling edge is applied to the HT82V24 until the actual sample of the input signal is held. both cdsclk1 and cdsclk2 sample the input signal during the transition from high to low, so the sampling delay is measured from each clock s falling edge to the instant the actual internal sample is taken. internal register descriptions register name address data bits a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 configuration 0 0 0 0 don t care 3-ch cds on clamp voltage enable power down input range 1 byte out mux 0 0 1 0 rgb/ bgr red green blue 0 0 0 0 red pga 0 1 0 0 0 0 msb lsb green pga 0 1 1 0 0 0 msb lsb blue pga 1 0 0 0 0 0 msb lsb red offset 1 0 1 msb lsb green offset 1 1 0 msb lsb blue offset 1 1 1 msb lsb internal register map (adi mode) register name address data bits a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 configuration 0 0 0 1 clamp timing control 3-ch cds on clamp voltage enable power down input range output format mux 0 0 1 del rgb/ bgr red green blue posnneg vdel red pga 0 1 0 0 0 0 msb lsb green pga 0 1 1 0 0 0 msb lsb blue pga 1 0 0 0 0 0 msb lsb red offset 1 0 1 msb lsb green offset 1 1 0 msb lsb blue offset 1 1 1 msb lsb internal register map (wolfson mode)
HT82V24 rev. 1.00 6 september 7, 2005 configuration register the configuration register controls the HT82V24 s oper - ating mode and bias levels. bits d7 and d6 set the clamp timing in wm mode and there are don't care in adi mode. bit d5 will configure the HT82V24 for the 3-channel (high) mode of operation. setting the bit d4 high will enable the cds mode of operation, and setting this bit low will enable the sha mode of operation. bit d3 sets the dc bias level of the HT82V24 s input clamp. this bit should always be set high for the 4v clamp bias, unless a ccd with a reset feed through transient exceeding 2v is used. setting the bit d3 low, the clamp voltage is 3v. bit d2 controls the power-down mode. setting bit d2 high will place the HT82V24 into a very low power sleep mode. all register contents are retained while the HT82V24 is in the power-down state. setting bit d1 high will select the 3v input range, other - wise the 2v input range is selected. d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 don t care 3 channels cds operation clamp bias power-down input range 1 byte out (high-byte only) 1=on* 1=cds mode* 1=4v* 1=on 1=3v 1=on 0=off 0= sha mode 0=3v 0=off (normal)* 0=2v* 0=off* configuration register settings (adi mode) d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 1 clamp timing control 3 channels cds operation clamp bias power-down input range output format cdsref1 cdsref0 1=on* 1=cds mode* 1=4v* 1=on 1=3v 1=byte output 0* 0* 0=off 0= sha mode 0=3v 0=off (normal)* 0=2v* 0=nibble output*,** configuration register settings (wolfson mode) note: * power-on default value ** it needs d5=0, d0=0 to enable nibble output (1ch wm mode) bits d7 and d6 control the reset sample and clamp timing

reset sample and clamp timing (rs/cl) note: cdsref=(cdsref1,cdsref0)
HT82V24 rev. 1.00 7 september 7, 2005 - 6 7 8 8 ! 9 8 8 ! ) ' % 0 : & - 6 7 ; 9 ; / / ) ' % 0 : 2 bit d0 control the adc output cycle of the HT82V24. bit d8 selects the adc data output format selection. setting d8 high enables the wm mode data output format while setting bit d8 low enables the adi mode output data format. the one nibble data will output data to pins d7~d4 and 4 4 (wm) mode output the data format selected. the output format as the following table: d8 d0 adc output format 00 d5=1: 3-ch 8 2 (adi) d5=0: 1 or 2-ch 8 2 (adi) 01 d5=1: 3-ch 8 1 (adi) d5=0: 1 or 2-ch 8 1 (adi) 10 d5=0: 1-ch 4 4 (wm) 11 d5=1: 3-ch 8 2 (wm) d5=0: 1-ch 8 2 (wm) - 6 7 % ; 9 % ; - 6 7 % ; ) ' % 0 : 2 ) ' % 0 : 2 / 6 7 % ; mux register the mux register controls the sampling channel order and the 2-channel mode configuration in the HT82V24. bit d8 is used to set the output latency in adc clock pe - riod and is only valid when wm mode data output format is selected. bit d7 is used when operating in the 3-channel mode or the 2-channel mode. setting bit d7 high will sequence the mux to sample the red channel first, then the green channel, and then the blue channel. when in the 3-channel mode, the cdsclk2 rising edge always resets the mux to sample the red channel first (see timing diagrams). when bit d7 is set low, the chan - nel order is reversed to blue first, green second, and red third. the cdsclk2 rising edge will always reset the mux to sample the blue channel first. bits d6, d5 and d4 are used when operating in 1 or 2-channel mode. bit d6 is set high to sample the red channel. bit d5 is set high to sample the green channel. bit d4 is set high to sample the blue channel. the mux will remain station - ary during 1-channel mode. the two channel mode is selected by setting two of the channel select bits (d4~d6) high. the mux samples the channels in the or - der selected by bit d7. in wm mode, bits d0~d2 are used to control the sampling point delay option. bit d3 is used to select the rising or falling edge on the cdsclk1 input pin and generates an internal vsmp pulse. bits d0~d3 set to 0 in adi mode. d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 mux order channel select set to 0 1=r-g-b* 1=red* 1=green 1=blue 0=b-g-r 0=off 0=off* 0=off* mux register settings (adi mode)
HT82V24 rev. 1.00 8 september 7, 2005 d8 d7 d6 d5 d4 d3 d2 d1 d0 del mux order channel select cds edge detection select delay period select 1: delay by two adc clock 1=r-g-b* 1=red* 1=green 1=blue posnneg vdel 2 vdel 1 vdel 0 0: minimum latency* 0=b-g-r 0=off 0=off* 0=off* 0* 0* 0* 0* mux register settings (wolfson mode) note: * power-on default value d0~d3 and d8 are valid only at wm mode. - *
! " 3 * 5 2 2 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 4 % " , *
! " 3 * 5 2 2 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 2 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 2 4 % " , * 3 * 5 4 % " , * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * note: vdel=(vdel2, vdel1, vdel0)
HT82V24 rev. 1.00 9 september 7, 2005 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (v/v) gain (db) set to 0 set to 0 set to 0 msb lsb 1.0 1.039 . . . 5.57 6 0.0 0.33 . . . 14.9 15.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 . . . 1 1 0 0 1 1 0 0 1 1 0* 1 0 1 pga gain register settings note: * power-on default value offset registers there are three offset registers for use in individually programming the offset in the red, green, and blue channels. bits d8 through d0 control the offset range from 300mv to 300mv in 512 increments. the coding for the offset registers is sign magnitude, with d8 as the sign bit. the following table shows the offset range as a function of the bits d8 through d0. d8 d7 d6 d5 d4 d3 d2 d1 d0 offset (mv) msb lsb 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 . . . 1 0 0 . . . 1 0 0 1 0 0 1 0 0 1 0 0 1 0* 1 1 0 1 1 0 1.17 . . . 300 0 1.17 . . . 300 note: * power-on default value pga gain registers there are three pga registers for use in individually pro - gramming the gain in the red, green and blue channels. bits d8, d7 and d6 in each register must be set low, and bits d5 through d0 control the gain range in 64 incre - ments. see figure for a graph of the pga gain versus pga register code. the coding for the pga registers is a straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corre - sponding to the maximum gain setting (6x). the HT82V24 uses one programmable gain amplifier (pga) for each channel. each pga has a gain range from 1x (0db) to 6x (15.6db), adjustable in 64 steps. the figure shows the pga gain as a function of the pga register code. although the gain curve is approximately linear in db, the gain in v/v varies in nonlinear propor - tion with the register code, according to the following the equation: gain= 6 1 4.85x( 63 g 63 ) + - where g is the decimal value of the gain register con - tents, and varies from 0 to 63. / 2 1 2 & 2 2 / 2 2 " < % 3 % % % % % % % % % % % % % 4 " * . * % 3 % % % % % % % % % % % % % 4 pga gain transfer function
timing diagrams HT82V24 rev. 1.00 10 september 7, 2005 % 3 / 4 - - / - ) ' % 0 : 2 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; - ) % 3 / 4 % 3 / 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 ! % " ' 3 = % = % 4 > ! % 3
/ 4 > ! % 3
4 > ! % 3
& 4 / - / / / / + / ) % 3 / 4 % 3 / 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 3-channel cds mode timing - - / - ) ' % 0 : 2 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; % 3 / 4 % 3 / 4 % 3 4 % 3 4 ! % " ' 3 = % = % 4 > ! % 3
4 > ! % 3
& 4 > ! % 3
1 4 / / % 3 / 4 % 3 / 4 % 3 4 % 3 4 / / / / + - - % 3 4 % 3 4 2-channel cds mode timing / 2 0 1 & / 2 , - ) 6 . ? 8 6 $ serial write operation timing / 2 0 1 & / 2 , - ) * . ? 8 6 $ serial read operation timing part (a): 8 2 (adi) output format
HT82V24 rev. 1.00 11 september 7, 2005 - - / - ) ' % 0 : 2 6 7 % ; 9 % ; ! % " ' > ! % 3 4 > ! % 3
4 > ! % 3
/ 4 / / / / ) / + - - > ! % 3 4 6 7 % ; 9 % ; 6 7 % ; 9 % ; > ! % 3 4 > ! % 3 $ 4 > ! % 3 $ 4 > ! % 3 0 4 > ! % 3 0 4 1-channel cds mode timing % 3 / 4 - / - ) ' % 0 : 2 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; ) % 3 / 4 % 3 / 4 % 3 / 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 % 3 4 ! % " ' 3 = % = % 4 / - > ! % 3
/ 4 > ! % 3
4 % 3 / 4 - / / / 3-channel sha mode timing - / - ) ' % 0 : 2 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; 6 7 ; 9 ; % 3 / 4 % 3 / 4 % 3 4 % 3 4 % 3 / 4 % 3 / 4 % 3 4 % 3 4 / / / / + - - % 3 4 % 3 4 ! % " ' 3 = % = % 4 > ! % 3
4 > ! % 3
& 4 2-channel sha mode timing
part (b): wm mode output format at vdel=(0,0,0), posneg=1 (those diagrams are identical for both cds and sha operation) 3-ch 8 2 (wm) 1-ch 8 2 (wm) 1-ch 4 4 (wm) HT82V24 rev. 1.00 12 september 7, 2005 - / - ) ' % 0 : 2 6 7 % ; 9 % ; ! % " ' > ! % 3 4 > ! % 3
4 / / ) / + - - > ! % 3 4 6 7 % ; 9 % ; 6 7 % ; 9 % ; > ! % 3 4 > ! % 3 $ 4 > ! % 3 $ 4 > ! % 3 0 4 > ! % 3 0 4 1-channel sha mode timing - * ! % " ' 3 = % = % 4 ) ' % % 0 : 2 $ > / % 3 ? 4 5 2 ) ' % % 0 : 2 $ > / % 3 ? 4 5 1 % - % < 3-channel mode timing (select r-g-b mode) - * ! % " ' 3 = % = % 4 ) ' % % 0 : 2 $ > / % 3 ? 4 5 2 ) ' % % 0 : 2 $ > / % 3 ? 4 5 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 1 % - % < 1-channel mode timing (select r mode) - * ! % " ' % 3 4 ) ' % % 0 : & & > & % 3 ? 4 5 2 ) ' % % 0 : & & > & % 3 ? 4 5 1 % - % < 1-channel mode timing (select r mode)
application circuits the recommended circuit configuration for the 3-channel cds mode operation is shown in the figure below (adi mode data output format). the recommended input coupling capacitor value is 0.1 f. a single ground plane is recommended for the HT82V24. a separate power supply may be used for drvdd, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V24. the loading of the digital outputs should be minimized, either by using short traces to the digital asic, or by using exter - nal digital buffers. to minimize the effect of digital transients during major output code transitions, the falling edge of the cdsclk2 should occur in coincidence with or before the rising edge of adcclk. all 0.1 f decoupling capacitors should be located as close as possible to the HT82V24 pins. when operating in a single channel mode, the unused an - alog inputs should be grounded. note: for the 3-channel sha mode, all of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V24 without the use of coupling capacitors. the off - set pin should be grounded if the inputs to the HT82V24 are to be referenced to ground, or a dc offset voltage should be applied to the offset pin in the case where a coarse offset needs to be removed from the inputs. the analog input signals must already be dc-biased between 0v and 2v, if offset is connected to ground. HT82V24 rev. 1.00 13 september 7, 2005 / $ / 0 / / 1 / & / / / / / 2 $ 0 1 / & 1 0 $ 2 / & * * * " ) + + , * " * " + , + * * ) - , - . * - / - ) * * 0 % 3 4 1 & / 2 % 3 4 # $ % 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + * 1 * . * < % " ' 2 + 1 * ! # @ " ' ) ' ! " ' 2 + 2 + % " ' ! % " ' / 2 $ 0 1 & / / & 1 0 $ 2 * " ) + + , + , + * * ) - , * * * - * * 0 1 & # $ % 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + * 1 * . * < % " ' 2 + 1 * ! # @ " ' ) ' ! " ' 2 + 2 + 2 + / $ / 0 / / 1 / & / / / / / 2 $ 0 1 / & 1 0 $ 2 / & * * * " ) + + , * " * " + , + * * ) - , - . * - / - ) * * 0 % 3 4 1 & / 2 % 3 4 $ % 2 + 2 + 2 + 2 + 2 + 2 + 2 + * 1 * . * < % " ' 1 * ! # @ " ' ) ' ! " ' % " ' ! % " ' % a ! / 2 $ 0 1 & / / & 1 0 $ 2 * " ) + + , + , + * * ) - , * * * - * * 0 1 & $ % 2 + 2 + 2 + 2 + 2 + 2 + 2 + * 1 * . * < % " ' 1 * ! # @ " ' ) ' ! " ' 2 + % a !
package information 20-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 490 510 d92 104 e 50 f4 g32 38 h4 12
0 10 HT82V24 rev. 1.00 14 september 7, 2005 / 2 2 + b 6
20-pin ssop (209mil) outline dimensions symbol dimensions in mil min. nom. max. a 291 323 b 196 220 c9 15 c 271 295 d65 73 e 25.59 f4 10 g26 34 h4 8
0 8 HT82V24 rev. 1.00 15 september 7, 2005 / 2 2 + b 6
28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12
0 10 HT82V24 rev. 1.00 16 september 7, 2005 / $ 1 & + b 6
28-pin ssop (209mil) outline dimensions symbol dimensions in mil min. nom. max. a 291 323 b 196 220 c9 15 c 396 407 d65 73 e 25.59 f4 10 g26 34 h4 8
0 8 HT82V24 rev. 1.00 17 september 7, 2005 / $ 1 & + b 6
product tape and reel specifications reel dimensions sop 20w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ssop 20n (209mil) symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 16.8+0.3 0.2 t2 reel thickness 22.2 0.2 HT82V24 rev. 1.00 18 september 7, 2005 , , /
sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24+0.3 0.1 p cavity pitch 12 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 10.8 0.1 b0 cavity width 13.3 0.1 k0 cavity depth 3.2 0.1 t carrier tape thickness 0.3 0.05 c cover tape width 21.3 HT82V24 rev. 1.00 19 september 7, 2005 ? 2 + - 2 2 2
ssop 20n (209mil) symbol description dimensions in mm w carrier tape width 16+0.3 0.1 p cavity pitch 12 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 7.1 0.1 b0 cavity width 7.2 0.1 k0 cavity depth 2 0.1 t carrier tape thickness 0.3 0.05 c cover tape width 13.3 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24 0.3 p cavity pitch 12 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT82V24 rev. 1.00 20 september 7, 2005
HT82V24 rev. 1.00 21 september 7, 2005 copyright 2005 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

▲Up To Search▲

Price & Availability of HT82V24

	To Download HT82V24 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .